Thomas Sterling

Dr. Thomas Sterling received his Ph.D. as a Hertz Fellow from MIT in 1984 and has held research scientist positions with the Harris Corporation's Advanced Technology Department, the IDA Supercomputing Research Center, and the USRA Center of Excellence in Space Data and Information Sciences. In 1996, Dr.Sterling began a joint appointment with the NASA Jet Propulsion Laboratory and the California Institute of Technology. He is a Principle Scientist in the Jet Propulsion Laboratory's High Performance Computing group, and he is a Faculty Associate at the California Institute of Technology's Center for Advanced Computing Research.

For the last 20 years, Dr. Sterling has engaged in applied research in parallel processing hardware and software systems for high performance computing. He was a developer of the Concert shared memory multiprocessor, the YARC static dataflow computer, and the Associative Template Dataflow computer concept, and he has conducted extensive studies of distributed shared memory cache coherence systems.

In 1994, Dr. Sterling led the team at the NASA Goddard Space Flight Center that developed the first Beowulf-class PC clusters including the Ethernet networking software for the Linux operating system. In 1999, he co-authored the MIT Press book "How to Build a Beowulf".

Since 1994, Dr. Sterling has been a leader in the national Petaflops initiative, chairing two workshops on Petaflops systems development and chairing the subgroup on the Petaflops computing implementation plan for the President's Information Technology Advisory Committee. He chaired both the first and second Conferences on Enabling Petaflops Computing in 1994 and 1999. He is also an author of the book, "Enabling Technologies for Petaflops Computing" published by MIT Press in 1995.

Dr. Sterling is the Principal Investigator for the interdisciplinary Hybrid Technology Multithreaded (HTMT) architecture research project sponsored by NASA, NSA, NSF, and DARPA involving a collaboration of more than a dozen cooperating research institutions. The HTMT project is developing an adaptive, latency tolerant, Petaflops-scale computer employing superconductor, optical, and processor-in-memory technologies.

Dr. Sterling holds six patents, and was the winner of 1997 Gordon Bell Prize for Price Performance.


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