The number of transistors and other components on integrated circuits will double every year for the next 10 years. So predicted Gordon Moore, Fairchild Semiconductor’s R&D Director, in 1965.
“Moore’s Law” came true. In part, this reflected Moore’s accurate insight. But Moore also set expectations— inspiring a self-fulfilling prophecy.
Doubling chip complexity doubled computing power without significantly increasing cost. The number of transistors per chip rose from a handful in the 1960s to billions by the 2010s.
The Man Behind The “Law”
A Ph.D. in chemistry and physics, Gordon Moore joined Shockley Semiconductor in 1956, left with Robert Noyce and other Shockley colleagues to create Fairchild in 1957, and in 1968 co-founded Intel—serving in roles from Executive Vice President to Chairman/CEO. He became Chairman Emeritus in 1997.
Moore made his original prediction to encourage sales of ever more complex Fairchild Semiconductor chips. With new data, in 1975 he revised his prediction forecasting that IC density would double every two years. Meeting Moore’s timetable became the goal for engineers who design chips.
This is the first page of “Cramming more components onto integrated circuits,” the April 19, 1965 Electronics magazine article that introduced Moore’s Law.View Artifact Detail
Bigger Wafers, Cheaper Chips
As IC chips grew larger and more densely packed with smaller transistors, the wafers they were fabricated on also grew. This combination reduced the cost per transistor from several dollars in the early 1960s to cheaper than a grain of rice today.
During the 50-year progression shown here, the smallest physical element on an IC has shrunk from 50 microns (μ) — smaller than a human hair, which is 80-100 μ in diameter — to less than 0.1 μ. (One micron is one thousandth of a millimeter, or one millionth of a meter.)
Wafer, smallest component dimension: 50 - 20 µ
IC Package, 6 leads, Fairchild Semiconductor, US, TO-5 metal canView Artifact Detail
Wafer, smallest component dimension: about 10 µ
IC Package, 14 leads, Fairchild Semiconductor, US, Ceramic Dual-inline Package (DIP)View Artifact Detail
Wafer, smallest component dimension: about 3 µ
IC Package, 64 leads, Amcor-Anam, Korea, Wide-body Plastic DIPView Artifact Detail
Wafer, smallest component dimension: about 0.8 - 00.5 µ
IC Package, 100 leads, Indy, US, Quad surface mount packageView Artifact Detail
Wafer, smallest component dimension: about 16 µ
IC Package, 14 leads, Stewart Warner, US, Ceramic flat pack and carrierView Artifact Detail
Wafer, smallest component dimension: about 1.25 - 1 µ
IC Package, 68 leads, Pin-grid array (PGA) packageView Artifact Detail